Signal acquisition method and apparatus using integrated phase locked loop

ABSTRACT

A test and measurement apparatus and method wherein a software implemented phase lock loop recovers a clock signal associated with the received data signal, the recovered clock signal being used to do TIE measurement, to generate eye diagram and to do mask testing.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of commonly owned provisionalpatent application Serial No. 60/340,766, filed Dec. 12, 2001, which ishereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

[0002] The invention relates generally to signal analysis instrumentsand, more specifically, to a method and apparatus providing enhanceddata communications measurements.

BACKGROUND OF THE INVENTION

[0003] Signal acquisition devices such as digital storage oscilloscopes(DSOs) and the like are commonly used for a variety of timingmeasurements during the testing of telecommunications and datacommunications (telecom/datacom) SIGNALS. Common tests performed ontelecom/datacom signals include the generation of eye diagrams, masktesting and time interval error (TIE) testing. These tests are performedusing dedicated hardware and software within the DSO. If the data/clocksignals are accurate, then the tests work well.

[0004] An eye diagram is a visual overlay of multiple data symbols thatare aligned in time on a display device. Mask tests are similar to eyediagrams where only selected bit sequences are overlaid. Eye diagramsand mask tests contemporaneously display multiple short waveformsegments. Typically, the time alignment for each segment comes fromtriggering on a data signal edge. The TIE test is a skew (i.e., delay)measurement between the edges of the sampled signal (i.e., clock or datasignal) and the edges of a reference signal (i.e., data or clocksignal). TIE is typically a measurement made on real-time acquisitions,and reference clock or data edges come from a “best fit” calculation ofan ideal clock derived from the sampled signal.

[0005] A useful reference signal for many telecom-timing measurements isthe recovered clock from a Phase-Locked Loop (PLL). Many telecom/datacomstandards (e.g., FibreChannel) utilize PLL clock/data recovery as partof the specifications. Since the recovered clock/data is used as theideal clock/data in telecom/datacom implementations, timing errors(i.e., Jitter) relative to the recovered clock are more appropriate thantiming errors relative to some other reference. A recovered clock signalfrom an external hardware PLL clock/data recovery circuit may be used totrigger the acquisition and display (e.g., eye diagram generation) ofdata received via a first oscilloscope input channel as well as be usedas reference clock signal for TIE measurement (via input of the clocksignal input to a second oscilloscope input channel). Internal hardwarePLL clock/data recovery circuit has been implemented for trigger, butnot suitable for TIE measurements since the recovered clock is notrecorded.

SUMMARY OF INVENTION

[0006] These and other deficiencies of the prior art are addressed bythe present invention of a method and apparatus for recovering a clockcomponent of a data signal using a phase locked loop to a test andmeasurement device.

[0007] Specifically, an apparatus according to one embodiment of theinvention comprises an acquisition unit, for acquiring at least aportion of a data signal in response to a trigger signal and providingtherefrom an acquired sample stream; a controller, including a memoryfor storing a phase locked loop (PLL) program, a processor for executingthe PLL program, and an input/output (I/O) circuit or program interfacefor receiving the acquired sample stream for use by the PLL programs andresponsively providing a clock signal recovered using the PLL program.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The teachings of the present invention can be readily understoodby considering the following detailed description in conjunction withthe accompanying drawings, in which:

[0009]FIG. 1 depicts a high level block diagram of a signal acquisitionsystem according to an embodiment of the present invention;

[0010]FIG. 2 depicts a high-level block diagram of a phase locked loop(PLL) suitable for use in the present invention;

[0011]FIG. 3 depicts a high level block diagram of a controller suitablefor use in the signal analysis system of FIG. 1; and

[0012]FIG. 4 depicts a flow diagram of a method according to anembodiment of the invention.

[0013] To facilitate understanding, identical reference numerals havebeen used, where possible, to designate identical elements that arecommon to the figures.

DETAILED DESCRIPTION OF THE INVENTION

[0014] The subject invention will be primarily described within thecontext of test and measurement devices such as digital storageoscilloscopes (DSOs). However, it will be appreciated by those skilledin the art that the invention may be advantageously employed in anyenvironment processing a signal having a clock or data component that isrecoverable using a phase locked loop.

[0015] Within the context of a test and measurement instrument, part ofthe invention resides in the recognition by the inventors recognizedthat a software phase lock loop may be implemented to perform thefunctions described above. Another part of the invention resides in anenhancement to an internal hardware PLL embodiment wherein the recoveredclock generated from the internal hardware PLL is recorded and, thus,usable for TIE measurements.

[0016]FIG. 1 depicts a high level block diagram of a signal acquisitionsystem according to an embodiment of the present invention.Specifically, the system 100 of FIG. 1 depicts portions of a digitalstorage oscilloscope (DSO) including portions relevant to the presentinvention. Those portions not specifically represented in FIG. 1 (e.g.,additional channels and the like) may readily be incorporated into thesystem 100 of FIG. 1 by those skilled in the art and informed by theteachings of the present invention.

[0017] The system 100 of FIG. 1 comprises, in part, a firstanalog-to-digital (A/D) converter 110 ₁, a first acquisition unit 120 ₁,a processing and display controller 130, a trigger circuit 140 and aninput unit 160.

[0018] The first A/D converter 110 ₁ receives a data signal DATA1 andresponsively produces a digitized data signal DATA1′ which is coupled tothe first acquisition unit 120. The first acquisition unit 120 ₁comprises, illustratively, at least one decimator as well as supportingacquisition memory. The first acquisition unit 120 ₁ is responsive to atrigger signal T to acquire at least portions of the digitized signalDATA1′, which portions are then provided to the processing and displaycontroller 130 as a first acquired sample stream AS₁.

[0019] The processing and display controller 130 comprises,illustratively, a display device (not shown) and associated dataprocessing circuitry suitable for converting the acquired sample streamsinto visual imagery. The processing and display unit 130 maycontemporaneously display a first vector or raster associated with thedata signal acquired by the acquisition unit 120, and a second vector orraster associated with a clock signal and use such displayed data toachieve a desired testing purpose.

[0020] The processing and display unit 130 is responsive to the inputunit 160 to set various parameters such as volts per division, timescale and the like. The processing and display unit 130 includes a timeinterval error (TIE) testing function 132, an eye generation function134 and a mask testing function 136. The TIE function 132 operates touse both acquired data and recovered clock to realize a TIE testingfunction. The eye diagram generation function 134 operates to generateeye diagrams using the data and clock components of the received datasignal DATA. The mask testing function 136 operates to generate an eyediagram representing a selected bit sequence. Other testing and displayfunctions may also be implemented.

[0021] The processing and display unit 130 also includes a softwareimplemented phase locked loop (PLL) function 138. The PLL function 138recovers from the acquired sample stream AS₁ a clock signal associatedwith that sample stream. The clock signal is used by the various testingand display functions as appropriate.

[0022] The input unit 160 comprises a keypad, a pointing device or othermeans adapted to provide user input to the controller 150. Thecontroller 150, in response to such user input, adapts the operations ofthe data acquisition unit(s) 120 to perform various data acquisition,triggering, processing, display and other functions. In addition, userinput may be used to trigger automatic calibration functions and/oradapt other operating parameters.

[0023] The trigger circuit 140 operates to produce the trigger signal Tthat is used by the first acquisition unit 120 ₁ to enable acquisitionof at least portions of the digitized data signal DATA1′.

[0024] The portions of FIG. 1 thus far described comprise those systemfunctions associated with a first embodiment of the invention; namely,the use of a software phase lock loop (PLL) function executed within thecontroller 130 to generate a clock signal based upon a received anddigitized data signal to enable thereby various test and measurementfunctions to be performed. Various test, measurement and displayfunctions associated with this and other embodiments will be describedin more detail below with respect to FIGS. 2-4.

[0025] In one embodiment, the trigger circuit 140 recovers from theinput data signal DATA1 (or a second input signal DATA2) a clock signalthat is subsequently used as the trigger signal T. This clock signal maybe generated using a hardware implementation of a PLL within the triggercircuit itself. The recovered clock generated from internal hardware PLLcircuit is optionally recorded by a second acquisition unit 120 ₁ forpost processing operations such as eye diagram generation, mask diagramgeneration and as reference signal for TIE measurements.

[0026] Specifically, in various embodiments of the invention, the system100 of FIG. 1 further comprises a second channel input select switch105, a second A/D converter 110 ₂ and a second acquisition unit 120 ₂.The second channel input select switch 105, in response to a controlsignal C1 produced by the controller 130, couples one of a second inputdata signal DATA2 and the clock recovered by a PLL within the triggercircuit 140 to the second A/D converter 110 ₂. The second AND converter110 ₂ responsively produces a digitized data signal DATA2′ which iscoupled to the second acquisition unit 120 ₂. The second acquisitionunit 120 ₂ comprises, illustratively, at least one decimator as well assupporting acquisition memory. The second acquisition unit 120 ₂ isresponsive to the trigger signal T to acquire at least portions of thedigitized signal DATA2′, which portions are then provided to theprocessing and display controller 130 as a second acquired sample streamAS₂.

[0027] Where the first acquired sample stream AS, comprises the datasignal DATA1′ and the second acquired sample stream AS₂ comprises theclock signal CLOCK, the controller 130 responsively uses these acquiredsample streams to perform any of the various testing and displayfunctions as described herein.

[0028] The trigger circuit 140 comprises, in one embodiment, a firsttrigger select switch 142, a hardware PLL 144, a second trigger selectswitch 146 and a trigger module 148. The first trigger select switch142, in response to a control signal C2 produced by the controller 130,couples one of an external trigger signal EXT TRIG and the first inputdata signal DATA1 (or second input data signal DATA2) to the hardwarePLL 144 and to an input of the second trigger select switch 146. Thehardware PLL 144 operates to generate a clock signal in response to thedata signal DATA1 or external trigger signal EXT TRIG. The resultingclock signal is coupled to an input of the second trigger select switch146 and channel input switch 105. The second trigger select switch 146,in response to a control signal C3 produced by the controller 130,couples one of its input signals to the trigger module 148, whichresponsively produces the trigger signal T that is coupled to one orboth of the first 120 ₁ and second 120 ₂ acquisition units.

[0029] The trigger module 148 optionally operates in one or more of aplurality of operating modes. In one mode, the trigger module 148comprises analog trigger circuitry and is responsive to an analog inputsignal, such as the input data signal DATA. In another mode, the triggermodule 148 comprises digital trigger circuitry and is responsive to adigital input signal, such as the digitized input data signal DATA1′ (orsecond digitized data signal DATA2′). In any mode (or combinationthereof), the trigger circuit 140 may be responsive to or implement thePLL function 144.

[0030] It will be appreciated by those skilled in the art that standardsignal processing components (not shown) such as signal bufferingcircuitry, signal delay or conditioning circuitry and the like are alsoemployed as appropriate to enable the various functions describedherein. For example, the A/D converter 110 samples its analog inputstream at a sufficiently high rate to enable appropriate processing bythe acquisition unit 120.

[0031] The system 100 of FIG. 1 is especially well adapted to accept adata or communications signal which has associated with it a clocksignal that may be extracted using a phase lock loop (PLL) clockrecovery technique. Such communications signals may comprise,illustratively, data signals conforming to a telecommunications and/ordata communications standard such as, for example, the fiber channelstandard and other serial data transform standards.

[0032]FIG. 2 depicts a high level block diagram of a phase lock loop(PLL) suitable for use in the present invention. The PLL 200 of FIG. 2comprises a functional diagram that is implemented as a software PLL(SWPLL) within the processing and display unit 130 or as hardware(HWPLL) within the hardware PLL 144. Briefly, an edge indicative signalsuch as acquired sample stream AS is applied to a phase detector 210along with a recovered clock signal. The phase detector 210 detectssignal edges and, in response to phase differences between the applieddata signal AS and a recovered clock signal CLOCK, produces a phaseerror indicative signal P_(ERROR). A loop filter 220 filters the phaseerror indicative signal P_(ERROR) to responsively produce an outputsignal indicative of the magnitude of the phase error (and smoothed intime to avoid spurious phase adjustments). The filtered phase errorsignal is applied to a voltage controlled oscillator (VCO or virtual VCOsuch as a clock generator) 230, which produces at its output therecovered clock signal CLOCK provided to the phase detector 210. As thephase error increases in magnitude, the magnitude of error indicated bythe loop filter increases and the oscillatory output of the VCO/clockgenerator 230 changes in a manner tending to reduce the detected phaseerror P_(ERROR). The reduction of phase error is determined by bandwidthand other parameters of the PLL. In this manner, the recovered clocksignal CLOCK is locked in phase to the received data signal AS andrepresents a clock signal associated with the received data signal.

[0033]FIG. 3 depicts a high level block diagram of a control circuitsuitable for use in the signal analysis system of FIG. 1. Specifically,the control circuit 300 of FIG. 3 may be employed to implement theprocessing and display unit 130.

[0034] The control circuit 300 of FIG. 3 comprises a processor 330 aswell as memory 340 for storing various control programs and otherprograms 342. The processor 330 cooperates with conventional supportcircuitry 320 such as power supplies, clock circuits, cache memory andthe like as well as circuits that assist in executing the softwareroutines stored in the memory 340. As such, it is contemplated that someof the steps discussed herein as software processes may be implementedwithin hardware, for example as circuitry that cooperates with theprocessor 330 to perform various steps. The control circuit 300 alsocontains input/output (I/O) circuitry 310 that forms an interfacebetween the various functional elements communicating with the functionimplemented using the control circuit 300.

[0035] Although the control circuit 300 of FIG. 3 is depicted as ageneral-purpose computer that is programmed to perform various controlfunctions in accordance with the present invention, the invention can beimplemented in hardware as, for example, an application specificintegrated circuit (ASIC), or a field programmable gate array (FPGA). Assuch, the process steps described herein are intended to be broadlyinterpreted as being equivalently performed by software, hardware, or acombination thereof.

[0036] The memory 340 is used to store the software instructionsnecessary to implement the PLL function 132. In this embodiment ofcontroller 130, the I/O circuit 310 receives the acquired sample streamAS₁ and responsively produces a software derived clock signal CLOCKwhich is used to perform various test, measurement and displayfunctions. It is noted that appropriate delay and/or sequencing isprovided to ensure that the processing delay incurred by the acquisitionunit 120 ₁ is compensated for, thereby allowing the display oftemporally aligned data and clock signals.

[0037] Specifically, a phase detector program 152-PD implements a phasedetection function, a loop filter program 152-LF implements a loopfilter function and a clock generator function 152-CG implements a clockgeneration (virtual PLL voltage controlled oscillator (VCO)) function asdiscussed above with respect to FIG. 2. The phase detector program152-PD is a software module that produces an output word or quantityhaving a magnitude proportional to the phase difference between its twoinput words or quantities. The phase detector program 152-PD may alsofunction as a phase/frequency detector. The loop filter program 152-LFcan be realized as, illustratively, an active proportional plus integral(PI) filter. In this realization, given a desired bandwidth theparameters of a corresponding Pi filter may be readily determined asknown to those skilled in the art. The clock generator function 152-CGcomprises, illustratively, a sine wave generator, square wave or otherfunction generator. A starting frequency and phase of a sine wavegenerated thereby can be based on explicit input from a user, acalculation of a best fitting slope (frequency) an offset (phase) to theedge times of an input clock and the like. The data and recovered clocksignals/words are normalized for use by the phase detector program152-PD such that the resulting calculated phase error signal/word isappropriate.

[0038] The memory 340 as shown also includes at least the softwareinstructions necessary for executing the TIE function 132, eye diagramgeneration function 134 and mask testing function 136. In thisembodiment of processing and display unit 130, the I/O circuit 310utilizes the recovered clock signal CLOCK and the acquired sample streamAS₁ and responsively produces the imagery associated with the TIEfunction 132, eye diagram generation function 134 and mask testingfunction 136.

[0039] The time interval error (TIE) testing function 132 is a skew(i.e., delay) measurement between the edges of the acquired signal ASand the edges of the clock signal CLOCK retrieved via the software PLLfunction 152. The TIE function may be implemented in a known manner bythose skilled in the art.

[0040] The eye diagram generation function 134 is implemented accordingto a software routine (unlike existing hardware implementations) thatgenerates a visual overlay of multiple data symbols that are aligned intime on the display device. Briefly, the acquired samples stream AS issliced into a sequence of frames using the clock signal CLOCK producedby the PLL function 152. The frames are stored in display memory in aframe-aligned manner to form thereby an eye diagram on the displaydevice. The mask testing function 136 is implemented in a manner similarto that described for the eye diagram function 134, except that onlyselected bit sequences are overlaid.

[0041]FIG. 4 depicts a flow diagram of a method according to anembodiment of the invention. Specifically, the method 400 of FIG. 4implements the software phase lock loop embodiment discussed above. Themethod 400 is entered at step 404, where the data edges within theacquired sample stream AS are determined. At step 405, the loop filterparameters, frequency and phase parameters of the VCO function areinitialized. At step 410, a determination is made as to whether moreinput data edges are to be received. If the query is answerednegatively, the method 400 is exited at step 415. Otherwise, at step 420the next input data edge is retrieved. That is, at step 420, the controlcircuit 300 determines that an input data edge on the received datasignal DATA₁′ is present.

[0042] At step 425, the phase detector function 152-PD computes a phaseerror. It is noted that the phase error computed assumes that a clockhas been previously recovered by the clock change program 152-CC.

[0043] At step 430, a determination is made as to whether the frequencyshould be updated. That is, at step 430 the phase error computed by thephase detector function 152-PD is used to determine whether the outputclock signal CLOCK generated by the controller (e.g., by toggling anoutput port signal or via a programmable timer or function generatorsuch as a sine wave or square wave generator) should be adjusted infrequency. If such adjustment should be made, then the loop filterfunction 152-LF computes a new output frequency of an output signalprovided by the controller. The controller output signal represents theclock signal CLOCK and is generated by toggling an output port bit,providing an output of a programmable timer or the like.

[0044] At step 440, the clock change function 152-CC computes the phaseand/or frequency output of the virtual VCO. At step 445, a determinationis made as to whether the next data edge should be retrieved. If thequery at step 445 is answered negatively, then the method 400 repeats atstep 440. Otherwise, the method 400 proceeds to step 410.

[0045] It will be appreciated by those skilled in the art that theabove-described SW-PLL is depicted as operating in a substantially “inlock” condition. Prior to achieving the in lock condition the method 400operates in a clock acquisition mode wherein the SW-PLL output is notrepresentative of a recovered clock signal. Upon achieving the in lockcondition, the SW-PLL output does represent the recovered clock signaland is useful as the clock signal CLOCK in the above embodiments of theinvention.

[0046] The SW-PLL of the present invention embodiment (in comparison toa hardware PLL) advantageously provides increased flexibility, since thevarious PLL parameters may be readily changed in software. Moreover, ahigher loop bandwidth is achieved since the highest data rate limitdepends upon the scope acquisition bandwidth, not the bandwidth of ahardware based PLL. In one embodiment, the SW-PLL works on singleacquisitions, so trigger jitter is automatically avoided. The SW-PLLembodiment also avoids the channel-to-channel sample jitter problemsince there is no requirement for a second channel and, therefore, noadditional jitter source. The SW-PLL is not affected by temperaturechange and power supply change as hardware PLL does. Finally, since theSWPLL configuration may perform more sophisticated computing operationsand use more precise data representations, greater accuracy is achieved.These advantages are gained at the expense of slower processing speed(the SWPLL requires post processing) and increased memory requirements.These embodiments will now be discussed in more detail.

[0047] While the foregoing is directed to the preferred embodiment ofthe present invention, other and further embodiments of the inventionmay be devised without departing from the basic scope thereof, and thescope thereof is determined by the claims that follow.

What is claimed is:
 1. Apparatus, comprising: an acquisition unit, foracquiring at least a portion of a data signal in response to a triggersignal and providing therefrom an acquired sample stream; and acontroller, including a memory for storing a phase locked loop (PLL)program, a processor for executing said PLL program, and an input/output(1/0) circuit for receiving said acquired sample stream for use by saidPLL programs and responsively providing a clock signal recovered usingsaid PLL program.
 2. The apparatus of claim 1, wherein said memoryfurther stores an eye diagram generation program operative to segmentsaid acquired sample stream into a plurality of frames according to saidrecovered clock signal and store said frames in a display memory.
 3. Theapparatus of claim 1, wherein said memory further stores an mask diagramgeneration program operative to segment said acquired sample stream intoa plurality of selected bit sequences according to said recovered clocksignal and store said bit sequences in a display memory.
 4. Theapparatus of claim 1, wherein said memory further stores a timinginterval error (TIE) program operative to process said acquired samplestream and said recovered clock signal according to a TIE function. 5.The apparatus of claim 1, wherein said trigger signal is generated inresponse to said recovered clock signal.
 6. The apparatus of claim 1,wherein said apparatus is included within an oscilloscope.
 7. Theapparatus of claim 1, wherein said data signal and recovered clocksignal are displayed on a display device as one of an eye diagram, amask function and a TIE function.
 8. An oscilloscope, comprising: ananalog to digital (A/D) converter for digitizing a data signal; anacquisition unit, for acquiring at least a portion of a digitized datasignal in response to a trigger signal; and a phase locked loop (PLL),adapted to recovering a clock signal from said data signal and a displaydevice, for contemporaneously displaying said data signal and said clocksignal.
 9. The oscilloscope of claim 8, wherein said PLL comprises ahardware PLL.
 10. The oscilloscope of claim 8, wherein said PLLcomprises a software PLL.
 11. The oscilloscope of claim 8, wherein adifference between said data signal and corresponding recovered clocksignal is displayed on a display device as a Time Interval Error (TIE)function.
 12. The oscilloscope of claim 8, wherein said trigger signalis generated in response to said recovered clock signal.
 13. A method,comprising: adapting a generated clock signal in response to a phasedifference between the generated clock signal and a corresponding datasignal; acquiring at least a portion of said data signal in response tosaid generated clock signal; and displaying at least one of an eyediagram, a mask diagram and a Time Interval Error (TIE) diagram usingsaid generated clock signal and said acquired portion of said datasignal.